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logisim-evolution
Table of contents Features Requirements Downloads Package Manager Nightly builds (unstable) Pictures of Logisim-evolution More Information Bug reports & feature requests For developers How to contribute Credits
OpenXiangShan
Open-source high-performance RISC-V processor
chipsalliance
Chisel: A Modern Hardware Design Language
YosysHQ
This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
chipsalliance
This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core. For more information on Rocket Chip, please consult our technical report.
verilator
Verilator open-source SystemVerilog simulator and lint system
steveicarus
1. What is ICARUS Verilog? 2. Building/Installing Icarus Verilog From Source - Compile Time Prerequisites - Compilation - (Optional) Testing - Installation 3. How Icarus Verilog Works - Preprocessing - Parse - Elaboration - Optimization - Code Generation - Attributes 4.
ghdl
This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL).
The-OpenROAD-Project
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
cocotb
cocotb: Python-based chip (RTL) verification
ucb-bar
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
amaranth-lang
A modern hardware definition language and toolchain based on Python
SpinalHDL
- A language to describe digital hardware - Compatible with EDA tools, as it generates VHDL/Verilog files - Much more powerful than VHDL, Verilog, and SystemVerilog in its syntax and features - Much less verbose than VHDL, Verilog, and SystemVerilog - Not an HLS, nor based on…
chipsalliance
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
The-OpenROAD-Project
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
YosysHQ
nextpnr portable FPGA place and route tool
Docs | Quick Start [](https://bit.ly/learn-xls) | Tutorials
olofk
Package manager and build abstraction tool for FPGA/ASIC development
chili-chips-ba
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
hughperkins
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
aappleby
A repository of gate-level simulators and tools for the original Game Boy.
siliconcompiler
SiliconCompiler is a modular hardware build system ("make for silicon"). The project philosophy is to "make the complex possible while keeping the simple simple".
gtkwave
GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
chipsalliance
This repository contains the VeeR EH1 design RTL.
nickg
NVC supports almost all of VHDL-2008 with the exception of PSL, and it has been successfully used to simulate several real-world designs. Experimental support for Verilog and VHDL-2019 is under development.
olofk
An abstraction library for interfacing EDA tools
JulianKemmerer
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
sergeykhbr
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
The-OpenROAD-Project
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
ben-marshall
A List of Free and Open Source Hardware Verification Tools and Frameworks
calyxir
Intermediate Language (IL) for Hardware Accelerator Generators
spcl
DaCe - Data Centric Parallel Programming
QKeras: a quantization deep learning library for Tensorflow Keras
The-OpenROAD-Project
OpenSTA is a gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats.
YosysHQ
SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
slaclab
A huge VHDL library for FPGA and digital ASIC development
m3rcer
A .NET XOR encrypted cobalt strike aggressor implementation for chisel to utilize faster proxy and advanced socks5 capabilities.
rggen
Code generation tool for control and status registers
pymtl
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
T-K-233
RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel
dpretet
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
chipsalliance
This is the top-level repository for the F4PGA project, which is a Workgroup under the CHIPS Alliance; consisting of members from different backgrounds, including FPGA vendors, industrial users and academia (see Documentation > Community); who collaborate to build a more open…
0BAB1
Learn how to build our own RV32I(M) core, verify it and actually use it. From scratch & with more than 200 pages of detailed tutorial with schemes & explanation.
librelane
ASIC implementation flow infrastructure, successor to OpenLane
efabless
Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
spcl
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
cornell-zhang
Allo Accelerator Design and Programming Framework (PLDI'24)
howerj
A Forth CPU and System on a Chip, based on the J1, written in VHDL
NNgen
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
zZedix
Modern tunnel management built on GOST, Backhaul, FRP, Chisel and Rathole, featuring an intuitive WebUI, fast CLI, and open-source freedom.
abdelazeem201
IC implementation of Systolic Array for TPU
spamegg1
Contact me: spamegg1 on Discord, or on Slack, or on Matrix
chipfoundry
The next generation of OpenLane, rewritten from scratch with a modular architecture
chipsalliance
VeeRwolf is a FuseSoC-based reference platform for the VeeR family of RISC-V cores. Currently, VeeR EH1 and VeeR EL2 are supported. See CPU configuration to learn how to switch between them.
definelicht
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
Lramseyer
Vaporview is an open source waveform viewer extension for VScode.
cornell-zhang
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)
chipsalliance
This repository contains the VeeR EL2 RISC-V Core design RTL.
ferrandi
The primary objective of the PandA project is to develop a usable framework that will enable the research of new ideas in the HW-SW Co-Design field.
PyHDI
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
f4pga
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
UCSBarchlab
A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
opiran-club
امکانات و کارهایی که انجام شده - SSH Tunnel (v4/6) - Iptables (v4/6) - Socat (v4/6) - WS tunnel (v4/6) - FRP (KCP-TCP) (v4/6) - Udp2raw (TCP-UDP) (v4/6) - Chisel Tunnel (v4/6) - Rathole tunnel (TCP-NOISE) (v4/6) - Private-IP /6to4 / native ipv6 setup (v4/6) - Tunnel broker setup…
SystemRDL
SystemRDL 2.0 language compiler front-end
raster-gpu
A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.
kactus2
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Azumi67
Establish a Reverse Tunnel between different servers and clients. IPV4 | IPV6 - Supports TCP & UDP . You can establish a tunnel between 5 Kharej servers & 1 IRAN server and vice versa.
apfaudio
A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.
ucb-bar
A Chisel RTL generator for network-on-chip interconnects
dpretet
Parametric AXI4 crossbar in SystemVerilog
Nic30
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
t3l3machus
A compact guide to network pivoting for penetration testings / CTF challenges.
suoto
Repurposing existing HDL tools to help writing better code
Juniper
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
lsils
Showcase examples for EPFL logic synthesis libraries
hdl-modules
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
SystemRDL
Control and status register code generator toolchain
ucsc-vama
Looking for RepCut, the parallelized version? Please check the repcut branch!
unblocked
Modern HTTPS reverse tunnels with live traffic capture and a simple dashboard.
cpc
Open Application-Specific Instruction Set processor tools (OpenASIP)
Eriemon
Agent skill for Verilog-2001 RTL generation and FPGA design workflows.
thousrm
hardware design of universal NPU(CNN accelerator) for various convolution neural network
arc-research-lab
CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
im-tomu
Support files for participating in a Fomu workshop
AUCOHL
Standard Cell Library based Memory Compiler using FF/Latch cells
chiselverify
A dynamic verification library for Chisel.
TimRudy
IceChips is a library of all common discrete logic devices in Verilog
cucapra
Time-sensitive affine types for predictable hardware generation
NYU-MLDA
OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.
ucb-bar
This repository contains the Chisel source RTL for the Saturn Vector Unit, a parameterized RVV 1.0 vector unit. Saturn supports the entire RVV 1.0 application-profile specification, including
getinstachip
VPM is a powerful package manager for Verilog projects, currently being piloted at Stanford and UC Berkeley. It's designed to streamline the management, reuse, and communication of IP cores and dependencies in hardware design workflows, significantly accelerating your design…
bogdanvuk
PyGears is a free framework that lets you design hardware using high-level Python constructs and compile it to synthesizable SystemVerilog or Verilog code. There is a built-in simulator that lets you use arbitrary Python code with its vast set of libraries to verify your…
FyraLabs
Use a VPS (or any other machine) as a reverse proxy for your Kubernetes cluster, without paying the extra 25$ a month!
fvutils
Python packages providing a library for Verification Stimulus and Coverage
najaeda
Netlist API (and more) for EDA flow development
loykylewong
《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
maltanar
A collection of Chisel hardware generators for small but useful components for FPGA projects.
mciepluc
Functional Coverage and Constrained Randomization Extensions for Cocotb
RadicalCSG
Chisel is an extension for Unity that allows for rapid, iterative, non destructive level editing!
KastnerRG
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
WilsonChen003
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
byuccl
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
lnis-uofu
The Logic Synthesis oracle is a framework developed on the top of EPFL logic synthesis libraries to unlock efficient logic manipulation by using different logic optimizers.To do so, the flow splits a design into different partitions and selects different optimizers for different…
polyphony-dev
Polyphony is Python based High-Level Synthesis compiler.
carlosedp
A RISC-V Core (RV32I) written in Chisel HDL
ttchisholm
For more information, refer to my blog series for this project - Designing a Low Latency 10G Ethernet Core - Part 1 (Introduction)
gipsyh
LLM-Assisted Hardware Formal Verification Tool
cornell-zhang
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
ymherklotz
A formally verified high-level synthesis tool based on CompCert and written in Coq.
cda-tum
An open-source design automation framework for Field-coupled Nanotechnologies
nbulsi
ALSO is based on the EPFL Logic Synthesis Libraries, we aim to exploit advanced logic synthesis tools for both modern FPGA and emerging nanotechnologies.
tomcl
Issie - an intuitive cross-platform hardware design application. https://tomcl.github.io/issie
hdl-registers
An open-source HDL register code generator fast enough to run in real time.
chipsalliance
Plugins for Yosys developed as part of the F4PGA project.
marcelwa
A Python library for working with logic networks, synthesis, and optimization.
raczben
HTML based waveform viewer for HDL simulators.
dpretet
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
Azumi67
Establishing a Direct tunnel using chisel between Servers and Client - IPV4 | IPV6 - TCP | UDP - [5] Kharej [1] IRAN
cocotb
Pre-packaged testbenching tools and reusable bus interfaces for cocotb
workcraft
Toolset to capture, simulate, synthesize and verify graph models
themperek
Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
TinyTapeout
Playground for VGA projects on Tiny Tapeout
Weiyet
Highly optimized (trying my best), synthesizable data structures module/IP library for hardware design
scale-lab
OpenPhySyn is a physical synthesis optimization kit developed at Brown University SCALE lab as part of the OpenROAD flow.
lsils
kitty is a C++-17 truth table library. It provides efficient implementations for basic truth table manipulations and various algorithms.
daquintero
Photonic Integrated ELectronics. Microservices to codesign photonics, electronics, quantum, and more.
SystemRDL
Generate address space documentation HTML from compiled SystemRDL input
SystemRDL
Generate UVM register model from compiled SystemRDL input
rameloni
A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code to values dumped by simulators is now possible thanks to Tywaves!
JeffDeCola
A place to keep my synthesizable verilog examples.
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